EP1S25F672C7

Product Summary

The EP1S25F672C7 contains a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provides signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks. The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the EP1S25F672C7.

Parametrics

EP1S25F672C7 absolute maximum ratings: (1)VCCINT Supply voltage With respect to ground: –0.5 to 2.4 V; (2)VCCIO: –0.5 to 4.6 V; (3)VI DC input voltage: –0.5 to 4.6 V; (4)IOUT DC output current, per pin: –25 to 25 mA; (5)TSTG Storage temperature No bias: –65 to 150 ℃; (6)TAMB Ambient temperature Under bias: –65 to 135 ℃; (7)TJ Junction temperature BGA packages under bias: 135 ℃.

Features

EP1S25F672C7 features: (1)10,570 to 114,140 LEs; (2)Up to 10,118,016 RAM bits (1,264,752 bytes) available without reducing logic resources; (3)TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers up to 312 MHz; (4)High-speed DSP blocks provide dedicated implementation of multipliers (at up to 250 MHz), multiply- accumulate functions, and finite impulse response (FIR) filters; (5)Up to 16 global clocks with 22 clocking resources per device region; (6)Up to 12 enhanced PLLs per device provide spread spectrum, programmable bandwidth, clock switch-over, real-time PLL reconfiguration, and advanced multiplication and phase shifting; (7)Support for numerous single-ended and differential I/O standards; (8)High-speed differential I/O support on up to 116 channels with up to 80 channels optimized for 840 megabits per second(Mbps); (9)TerminatorTM technology provides on-chip termination for differential and single-ended I/O pins with impedance matching; (10)Support for remote configuration updates.

Diagrams