TMS320C30GEL40

32-bit, floating-point processor, BGA

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Price:: US $200.00~220.00 / piece [Get Latest Price]

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	US $200.00~220.00

PartNumber:: TMS320C30GEL40

Brand:: Texas Instruments - TI | Pack: BGA | D/C: 88+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-07-29

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Part Number:TMS320C30GEL40
US $200.00 - 220.00
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US $20.00 - 25.00 / Piece
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Product Summary

The TMS320C30GEL40 is the newest member of the TMS320C3x generation of DSPs from Texas Instruments (TIE). The TMS320C30GEL40 is a 32-bit floating-point processor manufactured in 0.7-mm triple-level-metal CMOS technology. The TMS320C30GEL40 internal busing and special DSP instruction set have the speed and flexibility to execute up to 50 MFLOPS (million floating-point operations per second). The TMS320C30GEL40 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

Parametrics

TMS320C30GEL40 absolute maximum ratings: (1)Supply voltage range, VCC: –0.3 V to 7 V; (2)Input voltage range, VI: – 0.3 V to 7 V; (3)Output voltage range, VO: –0.3 V to 7 V; (4)Continuous power dissipation: 3.15 W; (5)Operating case temperature range, TC: 0℃ to 85℃; (6)Storage temperature range, Tstg: – 55℃ to 150℃.

Features

TMS320C30GEL40 features: (1)50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS; (2)32-Bit High-Performance CPU; (3)16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations; (4)32-Bit Instruction Word, 24-Bit Addresses; (5)Two 1K × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks; (6)One 4K × 32-Bit Single-Cycle Dual-Access On-Chip ROM Block; (7)On-Chip Memory-Mapped Peripherals: Two Serial Ports; Two 32-Bit Timers; One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation; (8)Two 32-Bit External Ports; (9)24- and 13-Bit Addresses; (10)Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation.