Product Summary

The ADSP-21161NCCAZ100 SHARC DSP is featuring Analog Devices Super Harvard Architecture. Easing portability, the ADSP-21161NCCAZ100 is source code compatible with the ADSP-21160 and with first generation ADSP-2106x SHARCs in SISD (Single Instruction, Single Data) mode. Like other SHARC DSPs, the ADSP-21161NCCAZ100 is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21161NCCAZ100 includes a 100 MHz core, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks.

Parametrics

ADSP-21161NCCAZ100 absolute maximum ratings: (1)Internal (Core) Supply Voltage (VDDINT): –0.3 V to +2.2 V; (2)Analog (PLL) Supply Voltage (AVDD): –0.3 V to +2.2 V; (3)External (I/O) Supply Voltage (VDDEXT): –0.3 V to +4.6 V; (4)Input Voltage: –0.5 V to VDDEXT + 0.5 V; (5)Output Voltage Swing: –0.5 V to VDDEXT + 0.5 V; (6)Load Capacitance: 200 pF; (7)Storage Temperature Range: –65℃ to +150℃.

Features

ADSP-21161NCCAZ100 features: (1)100 MHz (10 ns) Core Instruction Rate; (2)Single-Cycle Instruction Execution, Including SIMD Operations in Both Computational Units; (3)600 MFLOPs Peak and 400 MFLOPs Sustained Performance; (4)225-Ball 17 mm × 17 mm MBGA Package.

Diagrams

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