ADSP-21369KBPZ

Product Summary

The ADSP-21369KBPZ SHARC processor is member of the SIMD SHARC family of DSPs that feature Analog Devices Super Harvard Architecture. The ADSP-21369KBPZ is source code-compatible with the ADSP-2126x and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data)mode. The processors are 32-bit/40-bit floating point processors optimized for high performance automotive audio applications with its large on-chip SRAM, and mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface (DAI).

Parametrics

ADSP-21369KBPZ absolute maximum ratings: (1)Internal (Core) Supply Voltage (VDDINT): –0.3V to +1.5 V; (2)Analog (PLL) Supply Voltage (AVDD): –0.3V to +1.5 V; (3)External (I/O) Supply Voltage (VDDEXT): –0.3V to +4.6V; (4)Input Voltage: –0.5 V to +3.8 V; (5)Output Voltage Swing: –0.5 V to VDDEXT+ 0.5 V; (6)Load Capacitance: 200 pF; (7)Storage Temperature Range: –65℃ to +150℃; (8)Junction Temperature Under Bias: 125℃.

Features

ADSP-21369KBPZ features: (1)At 333 MHz (3 ns) core instruction rate, the processors perform 2 GFLOPS/666 MMACS; (2)2M bit on-chip, SRAM (0.75M bit in blocks 0 and 1, and ; (3)0.25M bit in blocks 2 and 3) for simultaneous access by the ; (4)core processor and DMA; (5)6M bit on-chip, mask-programmable ROM (3M bit in block 0 and 3M bit in block 1) ; (7)Dual data address generators (DAGs) with modulo and bitreverse addressing; (8)Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing; (9)Single-instruction, multiple-data (SIMD) architecture; (10)Two computational processing elements; (11)Concurrent execution; (12)Code compatibility with other SHARC family members at the assembly level; (13)Parallelism in buses and computational units allows: single cycle executions (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an instruction fetch; (14)Transfers between memory and core at a sustained; (15)6.4G bytes/s bandwidth at 333 MHz core instruction rate.

Diagrams