XC4VLX80-10FFG1148I

Product Summary

The XC4VLX80-10FFG1148I is the newest generation FPGA from Xilinx. The innovative Advanced Silicon Modular Block or ASMBL column-based architecture is unique in the programmable logic industry. XC4VLX80-10FFG1148I contains three families (platforms): LX, FX, and SX. Choice and feature combinations are offered for all complex applications. A wide array of hard-IP core blocks complete the system solution. These cores include the PowerPC. processors (with a new APU interface), Tri-Mode Ethernet MACs, 622 Mb/s to 11.1 Gb/s serial transceivers, voltage/temperature system monitor blocks, dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The XC4VLX80-10FFG1148I building blocks are an enhancement of those found in the popular Virtex-based product families: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, allowing upward compatibility of existing designs. XC4VLX80-10FFG1148I devices are produced on a state-of-the-art 90-nm copper process, using 300 mm(12 inch) wafer technology. Combining a wide variety of flexible features, the Virtex-4 family enhances programmable logic design capabilities and is a powerful alternative to ASIC technology.

Parametrics

XC4VLX80-10FFG1148I absolute maximum ratings: (1)VCCINT Internal supply voltage relative to GND: –0.5 to +2.7 V; (2)VCCO I/O supply voltage relative to GND: –0.5 to +4.0 V; (3)VCCJ JTAG I/O supply voltage relative to GND: –0.5 to +4.0 V; (4)VIN Input voltage with respect to GND: VCCO < 2.5V: –0.5 to +3.6 V; VCCO ≥ 2.5V: –0.5 to +3.6 V; (5)VTS Voltage applied to High-Z output: VCCO < 2.5V: –0.5 to +3.6 V; VCCO ≥ 2.5V: –0.5 to +3.6 V; (6)TSTG Storage temperature (ambient): –65 to +150℃; (7)TJ Junction temperature: +125℃.

Features

XC4VLX80-10FFG1148I features: (1)Xesium Clock Technology, Digital Clock Manager (DCM) blocks; (2)Additional Phase-Matched Clock Dividers (PMCD); (3)Differential Global Clocks; (4)XtremeDSP Slice, 18x18, two complement, signed Multiplier; (5)Optional pipeline stages; (6)Built-In Accumulator (48-bits) & Adder/Subtracter; (7)Smart RAM Memory Hierarchy; (8)Distributed RAM; (9)Dual-Port 18-Kbit RAM blocks; (10)Optional pipeline stages; (11)Optional programmable FIFO logic - Automatically remaps RAM signals as FIFO signals; (12)SelectIO Technology, 1.5 to 3.3 V I/O Operation; (13)Built-In ChipSync Source Synchronous Technology; (14)Digitally-controlled impedance (DCI) active termination; (15)Fine grained I/O banking (Configuration in one bank); (16)Flexible Logic Resources; (17)Built-in System Monitor (voltage/temp. measurement).

Diagrams